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1 february 9, 2009 idt72v73273 3.3 volt time slot interchange digital switch with rate matching 32,768 x 32,768 channels ? 2007 integrated device technology, inc. all rights reserved. product specifications subject to change without notice dsc-6140/4 idt and the idt logo are registered trademarks of integrated device technology, inc. the st-bus ? is a trademark of mitel corp. functional block diagram features: ? ? ? ? ? up to 64 serial input and output streams ? ? ? ? ? maximum 32,768 x 32,768 channel non-blocking switching ? ? ? ? ? accepts data streams at 2.048mb/s, 4.096mb/s, 8.192mb/s, 16.384mb/s or 32.768mb/s ? ? ? ? ? rate matching capability: rate selectable on both rx and tx in eight groups of 8 streams ? ? ? ? ? optional output enable indication pins for external driver high-z control ? ? ? ? ? per-channel variable delay mode for low-latency applications ? ? ? ? ? per-channel constant delay mode for frame integrity applications ? ? ? ? ? enhanced block programming capabilities ? ? ? ? ? tx/rx internal bypass ? ? ? ? ? automatic identification of st-bus ? ? ? ? ? and gci serial streams ? ? ? ? ? per-stream frame delay offset programming ? ? ? ? ? per-channel high-impedance output control ? ? ? ? ? per-channel processor mode to allow microprocessor writes to tx streams ? ? ? ? ? bit error rate testing (bert) for testing ? ? ? ? ? direct microprocessor access to all internal memories ? ? ? ? ? selectable synchronous and asynchronous microprocessor bus timing modes ? ? ? ? ? ieee-1149.1 (jtag) test port ? ? ? ? ? 208-pin (17mm x 17mm) plastic ball grid array (pbga) ? ? ? ? ? operating temperature range -40 c to +85 c description: the idt72v73273 has a non-blocking switch capacity of 32,768 x 32,768 channels at 32.768mb/s. with 64 inputs and 64 outputs, programmable per stream control, and a variety of operating modes the idt72v73273 is designed for the tdm time slot interchange function in either voice or data applications. some of the main features of the idt72v73273 are low power 3.3 volt operation, automatic st-bus ? /gci sensing, memory block programming, simple microprocessor interface , jtag test access port (tap) and per stream programmable input offset delay, variable or constant throughput modes, output enable and processor mode, ber testing, bypass mode, and advanced block programming. r x0-7 r x8-15 ode f32i v cc cs r/ w a0-a15 gnd dta/ beh d0-d15 tx0-tx7 tx8-15/oei0-7 ds c32i reset 6140 drw01 receive serial data streams mux data memory internal registers microprocessor interface timing unit connection memory transmit serial data streams jtag port tdo tms tdi tck tr st r x16-23 r x24-31 r x32-39 rx40-47 r x48-55 r x56-63 tx16-23 tx24-31/oei16-23 tx32-39 tx40-47/oei32-39 tx48-55 tx56-63/oei48-55 s/ a bel
2 industrial temperature range idt72v73273 3.3v time slot interchange digital switch with rate matching 32,768 x 32,768 channels a b c d e f g h j k l m n p r t c32i reset s/ a (1) f32i cs a2 a6 d3 d2 d1 d0 rx62 rx2 tx48 tx0 rx14 tx12/ oei4 tx14/ oei6 rx55 rx11 tx19 tx51 rx20 tx59/ oei51 rx15 rx1 tx52 rx4 tx54 tx63/ oei55 a12 rx59 tx16 tx18 tx20 tx25/ oei17 tx28/ oei20 rx24 12 34 56 7 8 910111213141516 a1 ball pad corner tx27/ oei19 tx30/ oei22 rx26 rx29 rx30 rx33 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd tx8/ oei0 rx5 a15 d14 d10 d7 rx60 rx61 tx15/ oei7 rx10 tx33 rx37 a9 a14 d15 d12 d8 d5 tms tck r/ w a3 a7 a10 dta/ beh a13 d13 d9 d6 d4 rx63 tx55 tx42/ oei34 tx43/ oei35 tx44/ oei36 rx27 rx32 rx35 rx39 tx35 tx39 rx52 rx48 rx44 tx45/ oei37 tx47/ oei39 rx41 rx19 tx17 rx23 tr st a0 a4 a8 a11 vcc rx0 tx1 tx6 rx3 tx2 rx6 rx9 tx9/ oei1 tx13/ oei5 tx10/ oei2 tx22 rx13 rx22 rx18 v cc ds tx3 rx7 rx8 v cc v cc v cc tx24/ oei16 rx12 rx21 rx17 v cc v cc rx36 tx32 tx36 rx43 rx42 rx16 tx31/ oei23 v cc v cc rx58 tx58/ oei50 tx62/ oei54 rx53 rx45 rx49 rx40 tx46/ oei38 rx31 rx34 rx38 tx34 tx38 tx41/ oe33 tx26/ oei18 tx29/ oei21 rx25 rx28 a1 a5 v cc v cc v cc v cc d11 bel v cc rx56 tx56/ oei48 tx60/ oei52 rx51 v cc v cc v cc rx47 rx57 tx53 tx57/ oei49 tx61/ oei53 rx50 tx50 rx54 tx49 rx46 tx40/ oei32 tx37 ode tx21 tx23 tdo tx5 tx11/ oei3 tx4 tx7 tdi 6140 drw0 3 pin configurations pbga: 1mm pitch, 17mm x 17mm (bb208-1 order code: bb) top view notes: 1. s/ a should be tied directly to vcc or gnd for proper operation.
3 industrial temperature range idt72v73273 3.3v time slot interchange digital switch with rate matching 32,768 x 32,768 channels pin description a0-a15 address 0-15 i *see pqfp *see pbga these address lines access all internal memories. table below table below bel byte enable low i 31 l4 in synchronous mode, this input will enable the lower byte (d0-7) on to the data bus. c32i clock i 2 a1 serial clock for shifting data in/out on the serial data streams. this input accepts a 32.768mhz clock. cs chip select i 12 e1 active low input used by a microprocessor to activate the microprocessor port of the device. d0-15 data bus 0-15 i/o *see pqfp *see pbga these pins are the data bus of the microprocessor port. table below table below ds data strobe i 11 d4 this active low input works in conjunction with cs to enable the read and write operations. this active low input sets the data bus lines (d0-d15). dta/beh data transfer i/o 32 k2 in asynchronous mode this pin indicates that a data bus transfer is complete. acknowledgment when the bus cycle ends, this pin drives high and then high-z allowing for active low output faster bus cycles with a weaker pull-up resistor. a pull-up resistor is required to /byte enable high hold a high level when the pin is high-z. when the device is in synchronous bus mode, this pin acts as an input and will enable the upper byte (d8-15) on to the data bus. f32i frame pulse i 3 b1 this input accepts and automatically identifies frame synchronization signals formatted according to st-bus ? and gci specifications. gnd *see pqfp *see pbga ground. table below table below ode output drive enable i 207 a3 this is the output enable control for the tx serial outputs. when ode input is low and the osb bit of the cr register is low, all tx outputs are in a high- impedance state. if this input is high, the tx output drivers are enabled. however, each channel may still be put into a high-impedance state by using the per channel control bits in the connection memory high. rx0-63 rx input 0 to 63 i *see pqfp *see pbga serial data input stream. these streams may have data rates of 2.048mb/s, table below table below 4.096mb/s, 8.192mb/s, 16.384mb/s, or 32.768mb/s depending upon the selection in receive data rate selection register (rdrsr). reset device reset: i 208 a2 this input (active low) puts the device in its reset state that clears the device internal counters, registers and brings tx0-63 and microport data outputs to a high-impedance state. the reset pin must be held low for a minimum of 20ns to reset the device. r/ w read/write i 13 e2 this input controls the direction of the data bus lines (d0-d15) during a microprocessor access. s/ a synchronous/ i 5 c1 this input will select between asynchronous microprocessor bus timing and asynchronous synchronous microprocessor bus timing. in synchronous mode, dta/beh bus mode acts as the beh input and is used in conjunction with bel to output data on the data bus. in asynchronous bus mode, bel is tied low and dta/beh acts as the dta, data bus acknowledgment output. tck test clock i 9 d2 provides the clock to the jtag test logic. tdi test serial data in i 7 c3 jtag serial test instructions and data are shifted in on this pin. this pin is pulled high by an internal pull-up when not driven. tdo test serial data out o 8 d1 jtag serial data is output on this pin on the falling edge of tck. this pin is held i in high-impedance state when jtag scan is not enabled. tms test mode select i 6 c2 jtag signal that controls the state transitions of the tap controller. this pin is pulled high by an internal pull-up when not driven. trst test reset i 10 d3 asynchronously initializes the jtag tap controller by putting it in the test- logic-reset state. this pin is pulled by an internal pull-up when not driven. this pin should be pulsed low on power-up, or held low, to ensure that the device symbol name i/o pqfp pbga description pin no. pin no.
4 industrial temperature range idt72v73273 3.3v time slot interchange digital switch with rate matching 32,768 x 32,768 channels pin description (continued) tx0-7 tx output o *see pqfp *see pbga serial data output stream. these streams may have data rates of 2.048mb/s, tx16-23 table below table below 4.096mb/s, 8.192mb/s,16.384mb/s, or 32.768mb/s depending upon the tx32-39 selection in transmit data rate selection register (tdrsr). tx48-55 tx8-15/oei0-7 tx output /output enable o *see pqfp *see pbga when output streams are selected via tdrsr, these pins are the tx output tx24-31/oei16-23 indication table below table below streams. when output enable indication function is selected, these pins reflect the tx40-47/oei32-39 active or high-impedance status for the corresponding tx output stream. tx56-63/oei48-55 v cc *see pqfp *see pbga +3.3 volt power supply.is in the normal functional mode. table below table below symbol name i/o pqfp pbga description pin no. pin no. pbga pin number table symbol name i/o description a0-a15 address a0-a15 i e3, e4, f1, f2, f3, f4, g1, g2, g3, h1, h2, h3, j3, j2, j1, k3. d0-d15 data bus 0-15 i/o t2, t1, r1, p1, p2, n1, n2, n3, m1, m2, m3, m4, l1, l2, l3, k1. gnd ground g7, g8, g9, g10, h7, h8, h9, h10, j7, j8, j9, j10, k7, k8, k9, k10. rx0-63 rx input 0 to 63 i b3, a4 , b4 , c4 , a5 , b5 , c5 , d5 , d11 , c11 , b11 , a11 , d12 , c12 , b12 , a12 , e13 , d13 , c13 , b13 , a13 , d14 , c14 , b14 , g16 , g15, g14 , h16 , h15 , h14 , j14 , j15 , j16 , k14 , k15 , k16 , l13, l14 , l15 , l16 , r14 , t13, r13 , p13 , t12 , r12 , p12 , n12 , t11 , r11 , p11 , n11 , t10 , r10 , p10 , t9, n4 , p4 , r4 , t4, p3 , r3 , t3 , r2 . tx0-7 tx output o a6, b6, ,c6 d6, a7, b7, c7, a8. tx16-23 a14, b15, a15, a16, b16, c16, c15, d16. tx32-39 m13, m14, m15, m16, n13, n14, n15, n16. tx48-55 r9, p9, p8, r8, t8, p7, r7, t7. tx8-15/oei0-7 tx output/output o b8, c8, c9, b9, a9, c10, b10, a10. tx24-31/oei16-23 d15, e16, e15, e14, f16, f15, f14, f13. tx40-47/oei32-39 p14, p15, p16, r16, t16, t15, r15, t14. tx56-63/oei48-55 n6, p6, r6, t6, n5, p5, r5, t5. vcc b2, d7, d8, d9, d10, g4, g13, h4, h13, j4, j13, k4, k13, n7, n8, n9, n10.
5 industrial temperature range idt72v73273 3.3v time slot interchange digital switch with rate matching 32,768 x 32,768 channels description (continued) the idt72v73273 is capable of switching up to 32,768 x 32,768 channels without blocking. designed to switch 64 kbit/s pcm or n x 64 kbit/s data, the device maintains frame integrity in data applications and minimizes throughput delay for voice applications on a per-channel basis. the 64 serial input streams (rx) of the idt72v73273 can be run at 2.048mb/s, 4.096mb/s, 8.192mb/s, 16.384mb/s or 32.768mb/s allowing 32, 64, 128, 256 or 512 channels per 125 s frame. the data rates on the output streams can independently be programmed to run at any of these data rates. with two main operating modes, processor mode and connection mode, the idt72v73273 can easily switch data from incoming serial streams (data memory) or from the controlling microprocessor via connection memory. as control and status information is critical in data transmission, the processor mode is especially useful when there are multiple devices sharing the input and output streams. with data coming from multiple sources and through different paths, data entering the device is often delayed. to handle this problem, the idt72v73273 has a frame offset feature to allow individual streams to be offset from the frame pulse in half clock-cycle intervals up to +7.5 clock cycles. the idt72v73273 also provides a jtag test access port, memory block programming, group block programming, rx/tx internal bypass, a simple microprocessor interface and automatic st-bus ? /gci sensing to shorten setup time, aid in debugging and ease use of the device without sacrificing capabilities. functional description data and connection memory all data that comes in through the rx inputs go through a serial-to-parallel conversion before being stored into internal data memory. the 8 khz frame pulse (f32i) is used to mark the 125 s frame boundaries and to sequentially address the input channels in data memory. data output on the tx streams may come from either the serial input streams (data memory) or from the connection memory via the microprocessor or in the case that rx input data is to be output, the addresses in connection memory are used to specify a stream and channel of the input. the connection memory is setup in such a way that each location corresponds to an output channel for each particular stream. in that way, more than one channel can output the same data. in processor mode, the microprocessor writes data to the connection memory locations corresponding to the stream and channel that is to be output. the lower half (8 least significant bits) of the connection memory low is output every frame until the microprocessor changes the data or mode of the channels. by using this processor mode capability, the microprocessor can access input and output time-slots on a per-channel basis. the three least significant bits of the connection memory high are used to control per-channel mode of the output streams. the mod2-0 bits are used to select processor mode, constant or variable delay mode, bit error rate, and the high-impedance state of output drivers. if the mod2-0 bits are set to 1-1-1 accordingly, only that particular output channel (8 bits) will be in the high- impedance state. if the mod2-0 bits are set to 1-0-0 accordingly, that particular channel will be in processor mode. if the mod2-0 bits are set to 1-0-1 a bit error rate test pattern will be transmitted for that time slot. see bert section. if the mod2-0 bits are set to 0-0-1 accordingly, that particular channel will be in constant delay mode. finally, if the mod2-0 bits are set to 0-0-0, that particular channel will be in variable delay mode. serial data interface timing the master clock frequency of the idt72v73273 is 32.768mhz, c32i. for 32.768mb/s data rates, this results in a single-bit per clock. for 16.384mb/s, 8.192mb/s, 4.096mb/s, and 2.048mb/s this will result in two, four, eight, and sixteen clocks per bit, respectively. the idt72v73273 provides two different interface timing modes, st-bus ? or gci. the idt72v73273 automatically detects the polarity of an input frame pulse and identifies it as either st-bus ? or gci. for 32.768mb/s, in st-bus ? mode, data is clocked out on a falling edge and is clocked in on the subsequent rising-edge. for 16.384mb/s, 8.192mb/s, 4.096mb/s, and 2.048mb/s however there is not the typical associated clock since the idt72v73273 accepts only a 32.768mhz clock. as a result there will be 2, 4, 8, and 16 clock between the 32.768mb/s transmit edge and the subsequently transmit edges. although in this is the case, the idt72v73273 will appropriately transmit and sample on the proper edge as if the respective clock were present. see st-bus ? timing for detail. for 32.768mb/s, in gci mode, data is clocked out on a rising edge and is clocked in on the subsequent falling-edge. for 16.384mb/s, 8.192mb/s, 4.096mb/s, and 2.048mb/s however, again there is not the typical associated clock since the idt72v73273 accepts only a 32.768mhz clock. as a result there will 2, 4, 8, and 16 clocks between the 32.768mb/s transmit edge and the other transmit edges. although this is the case, the idt72v73273 will appropriately transmit and sample on the proper edge as if the respective clock were present. see gci bus timing for detail. delay through the idt72v73273 the switching of information from the input serial streams to the output serial streams results in a throughput delay. the device can be programmed to perform time-slot interchange functions with different throughput delay capabilities on a per-channel basis. for voice applications, variable throughput delay is best as it ensure minimum delay between input and output data. in wideband data applications, constant throughput delay is best as the frame integrity of the information is maintained through the switch. the delay through the device varies according to the type of throughput delay selected in the mod bits of the connection memory. variable delay mode (mod2-0 = 0-0-0) in this mode, mostly for voice applications where minimum throughput delay is desired, delay is dependent on the combination of source and destination channels. the minimum delay achievable is a 3 channel periods of the slower data rate . constant delay mode (mod2-0 = 0-0-1) in this mode, frame integrity is maintained in all switching configurations by making use of a multiple data memory buffer. input channel data is written into the data memory buffers during frame n will be read out during frame n+2. in the idt72v73273, the minimum throughput delay achievable in constant delay mode will be one frame plus one channel. see table 14.
6 industrial temperature range idt72v73273 3.3v time slot interchange digital switch with rate matching 32,768 x 32,768 channels microprocessor interface the idt72v73273?s microprocessor interface looks like a standard ram interface to improve integration into a system. with a 16-bit address bus and a 16-bit data bus all memories can be accessed. using the tsi microprocessor interface, reads and writes are mapped into data and connection memories. by allowing the internal memories to be randomly accessed, the controlling microprocessor has more time to manage other peripheral devices and can more easily and quickly gather information and setup the switch paths. table 1 shows the mapping of the addresses into internal memory blocks. in order to minimize the amount of memory mapped space however, the memory select (ms1-0) bits in the control register must be written to first to select between the connection memory high, the connection memory low, or data memory. effectively, the memory select bits act as an internal mux to select between the data memory, connection memory high, and connection memory low. memory mapping the address bus on the microprocessor interface selects the internal registers and memories of the idt72v73273. the most significant bit of the address select between the registers and internal memories. see table 1 for mappings. as explained in the initialization sections, after system power-up, the tdrsr and rdrsr, should be programmed immediately to establish the desired switching configuration. the data in the control register consists of the software reset, rx/tx bypass, output enable polarity, all output enable, full block programming, block programming data, begin block programming enable, reset connection memory low in block programming, output standby, and memory select. software reset the software reset serves the same function as the hardware reset. as with the hard reset, the software reset must also be set high for 20ns before bringing the software reset low again for normal operation. once the software reset is low, internal registers and other memories may be read or written. during software reset, the microprocessor port is still able to read from all internal memories. the only write operation allowed during a software reset is to the software reset bit in the control register to complete the software reset. connection memory control if the ode pin and the output standby bit are low, all output channels will be in three-state. see table 2 for detail. if mod2-0 of the connection memory high is 1-0-0 accordingly, the output channel will be in processor mode. in this case the lower eight bits of the connection memory low are output each frame until the mod2-0 bits are changed. if mod2-0 of the connection memory high are 0-0-1 accordingly, the channel will be in constant delay mode and bits 14-0 are used to address a location in data memory. if mod2-0 of the connection memory high are 0-0-0, the channel will be in variable delay mode and bits 14-0 are used to address a location in data memory. if mod2-0 of the connection memory high are 1-1-1, the channel will be in high-impedance mode and that channel will be in three-state. rx/tx internal bypass when the bypass bit of control registers is 1, all rx streams will be ?shorted? to tx in effect bypassing all internal circuitry of the tsi. this effectively sets the tsi to a 1-to-1 switch mode with minimal i/o delay. a zero can be written to allow normal operation. the intention of this mode is to minimize the delay from the rx input to the tx output making the tsi ?invisible?. initialization of the idt72v73273 after power up, the state of the connection memory is unknown. as such, the outputs should be put in high-impedance by holding the ode pin low. while the ode is low, the microprocessor can initialize the device by using the block programming feature and program the active paths via the microprocessor bus. once the device is configured, the ode pin (or output standby bit depending on initialization) can be switched to enable the tsi switch.
7 industrial temperature range idt72v73273 3.3v time slot interchange digital switch with rate matching 32,768 x 32,768 channels table 1 ? address mapping 1 sta5 sta4 sta3 sta2 sta1 sta0 ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 r/ w internal 0x8000- memory 0xffff (cm, dm (read only) (1) 00 0 0 0 0 0 x xx xx xx xxr/ w control 0x00xx register 00 0 0 0 0 1 x xx xx xx xxr/ w tdrsr0 0x02xx 00 0 0 0 1 0 x xx xx xx xxr/ w tdrsr1 0x04xx 00 0 0 0 1 1 x xx xx xx xxr/ w rdrsr0 0 x06xx 00 0 0 1 0 0 x xx xx xx xxr/ w rdrsr1 0 x08xx 00 0 0 1 0 1 x xx xx xx xxr/ w bpsa 0x0axx 00 0 0 1 1 0 x xx xx xx xxr/ w bpea 0x0cxx 0 0 0 0 1 1 1 x x x x x x x x x r/w bis 0x0exx 0 0 0 1 0 0 0 x x x x x x x x x r/w ber 0x10xx 00 1 0 0 0 0 x xx xx xx xxr/ w for0 0 x20xx 00 1 0 0 0 1 x xx xx xx xxr/ w for1 0 x22xx 00 1 0 0 1 0 x xx xx xx xxr/ w for2 0 x24xx 00 1 0 0 1 1 x xx xx xx xxr/ w for3 0 x26xx 00 1 0 1 0 0 x xx xx xx xxr/ w for4 0 x28xx 00 1 0 1 0 1 x xx xx xx xxr/ w for5 0x2axx 00 1 0 1 1 0 x xx xx xx xxr/ w for6 0x2cxx 00 1 0 1 1 1 x xx xx xx xxr/ w for7 0x2exx 00 1 1 0 0 0 x xx xx xx xxr/ w for8 0 x30xx 00 1 1 0 0 1 x xx xx xx xxr/ w for9 0 x32xx 00 1 1 0 1 0 x xx xx xx xxr/ w for10 0 x34xx 00 1 1 0 1 1 x xx xx xx xxr/ w for11 0 x36xx 00 1 1 1 0 0 x xx xx xx xxr/ w for12 0 x38xx 00 1 1 1 0 1 x xx xx xx xxr/ w for13 0x3axx 00 1 1 1 1 0 x xx xx xx xxr/ w for14 0x3cxx 00 1 1 1 1 1 x xx xx xx xxr/ w for15 0x3exx a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 r/ w location hex value 1-1-1 1 x x per channel high-impedance any, other than 1-1-1 1 0 0 all tx in high-impedance any, other than 1-1-1 1 0 1 enable any, other than 1-1-1 1 1 0 enable any, other than 1-1-1 1 1 1 enable any, other than 1-1-1 0 x x group x of oex is in high-impedance mod2-0 bits in oe x bit of tdrsr ode pin osb bit in output driver status connection control register control register memory high table 2 ? output high-impedance control note: 1) select connection memory high, connection memory low, or data memory by setting the ms1-0 bits in the control register. note: x = don't care.
8 industrial temperature range idt72v73273 3.3v time slot interchange digital switch with rate matching 32,768 x 32,768 channels table 3 ? control register (cr) bits reset value: 0000 h 151413121110987654 321 0 bit name description 15 srs a one will reset the device and have the same effect as the reset pin. must be zero for normal operation. (software reset) 14 byp when the bypass bit is 1, all rx streams will be ?shorted? to tx -- in effect bypassing all internal circuitry of the tsi. this effectively (rx/tx bypass) sets the tsi to a 1-to-1 switch mode with almost only a few nanoseconds of delay. a zero can be written to allow normal operation. the intention of this mode is to minimize the delay from the rx input to the tx output making the tsi ?invisible?. any offset values in the for register will be required. 13 oepol when 1, a one on oei pin denotes an active state on the output data stream; zero on oei pin denotes high-impedance state. (output enable polarity) when 0, a one denotes high-impedance and a zero denotes an active state. oei mode is entered on a per- group basis in the drsr. 12 aoe when 1, all output stream pin (txn) become oei to allow for a two-chip solution for a larger switching matrix with oei pin s. when (all output enable) in aoe the drs must be set to the corresponding data rates of the other device. 11 prst when high, the prbs transmitter output will be initialized. (prbs reset) 10 cber a low to high transition of this bit clears the ber register (berr). (clear bit error rate) 9 sber a low to high transition in this bit starts the bit error rate test. the bit error test result is kept in the ber register (berr ). (start bit error rate) 8 fbp when 1, this bit overrides the bpsa and bpea registers and programs the full connection memory space. when 0, the bpsa (full block programming) and bpea determine the connection memory space to be programmed. 7-5 bpd2-0 these bits carry the value to be loaded into the connection memory block whenever the connection memory block programm ing (block programming data) feature is activated. after the bpe bit is set to 1 from 0, the contents of the bits bpd2-0 are loaded into bit 2, 1 and 0 (mod2-0) of the connection memory high. 4 bpe a zero to one transition of this bit enables the connection memory block programming feature delimited by the bpsa and bpea (begin block registers as well as for a full back program. once the bpe bit is set high, the device will program the connection memory block programming enable) as fast as than if the user manually programmed each connection memory location through the microprocessor. after the programming function has finished, the bpe bit returns to zero to indicate the operation has completed. when the bpe = 1, the bpe bit can be set to 0 to abort block programming. 3 rcml when r cml =1, all bits 14-0 in connection memory low will be reset to zero during block programming; when rcml=0, (reset connection bits 14-0 in connection memory low will retain their original values during block programming. memory low in block ` programming) 2 osb when ode = 0 and osb = 0, the output drivers of transmit serial streams are in high-impedance mode. when either ode = 1 (output standby) or osb = 1, the output serial stream drivers function normally. 1-0 ms1-0 these two bits decide which memory to be accessed via microprocessor port. (memory select) 00 -- connection memory low 01 -- connection memory high 10 -- data memory 11 -- reserved srs byp oepol aoe prst cber sber fbp bpd2 bpd1 bpd0 bpe rcml osb ms1 ms0
9 industrial temperature range idt72v73273 3.3v time slot interchange digital switch with rate matching 32,768 x 32,768 channels memory block programming the idt72v73273 provides users with the capability of initializing the entire connection memory block in two frames. to set bits 2,1 and 0 of every connection memory high location, set the full block program to 1, write the desired pattern in to the block programming data bits (bpd2-0), and enable the block program enable bit. all of the block programming control can be found in the control register. the block programming mode is enabled by setting the block program enable bit of the control register high. when the block programming enable bit of the control register is set to high, the block programming data will be loaded into the bits 2,1 and 0 of every connection memory high location regardless of the selected data rate for the group. the connection memory low bits will be loaded with zeros when the reset connection memory low(rcml) bit is enabled and is otherwise left untouched. when the memory block programming is complete, the device resets the block programming enable and the bpd2-0 bits to zero. the idt72v73273 also incorporates a feature termed group block programming. group block programming, allows subsections of the connection memory to be block programmed as if the microprocessor were accessing the connection memory high locations back-to-back fashion. this results in one connection memory high location being programmed for each 32i clock cycle. by having the tsi perform this function it allows the controlling microprocessor more time to perform other functions. also, the tsi can be more efficient in programming the locations since one cmh location is programmed every 32i clock cycle. the group block programming function programs "channel n" for all streams deliniated by the group before going to "channel n+1". a c-code representation is shown below. the group block programming feature is composed of the block programming start address(bpsa), the block program- ming end address(bpea), and the bpe and bpd bits in the control register. the bpsa contains a start address for the block programming and bpea contains an end address. the block programming will start at the start address and program until the end address even if the end address is ?less? than the start address. in other words there is no mechanism to prevent a start address that is larger than the end address. if this occurs, the inverse cm locations in the given group are programmed resulting in a ?wrap around? effect. this ?wrap around? effect is independent for both the stream and channel addresses. this is illustrated in the group block programming diagram see figure 1 group block programming. users must not initiate a block program too close (ahead) of the present transmit locations. if this is done the tsi may simultaneously access the cm location that is being modified and unpredictable data on tx outputs may occur. users should take care when using the group block programming feature. users must not initiate a block program too close (ahead) of the present transmit location. if this is done the tsi may simultaneously access the cm location that is being modified and unpredictable data on tx outputs may occur. it should be noted however, in order to enable the group block programming the full block program (fbp) must be 0.
10 industrial temperature range idt72v73273 3.3v time slot interchange digital switch with rate matching 32,768 x 32,768 channels table 4 ? block programming starting address (bpsa) register reset value: 0000 h 1514131211109876543210 15 unused must be zero for normal operation. 14-12 g2-0 these bits are used to select which group will be block programmed (group address bits 2-0) 11-9 sta2-0 these bits are used to select starting stream number for block programming. (stream address bits 2-0) 8-0 cha8-0 these bits are used to select starting channel number for block programming. (channel address bits 8-0) bit name description 0 g2 g1 g0 sta2 sta1 sta0 ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 table 5 ? block programming ending address (bpea) register 1514131211109876543210 reset value: ffff h 15-12 unused must be one for normal operation. 11-9 sta2-0 these bits are used to select ending stream number for burst programming. (stream address bits 2-0) 8-0 cha8-0 these bits are used to select starting channel number for burst programming. (channel address bits 8-0) bit name description 1 1 1 1 sta2 sta1 sta0 ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0
11 industrial temperature range idt72v73273 3.3v time slot interchange digital switch with rate matching 32,768 x 32,768 channels 6140 drw04 x x x channels xx streams x x 7 0,0 stream 2 stream 4 channel 20 channel 123 bpea = st2, ch123 bpsa = st4, ch20 255 xx x x x x x x x x x x channels xx streams x x 7 0,0 channel 20 channel 123 stream 4 stream 2 bpsa = st2, ch20 bpea = st4, ch 123 255 connection memory x x xx x x x x x x channels xx streams x x 7 0,0 channel 20 channel 123 stream 4 stream 2 bpsa = st4, ch12 3 bpea = st2, ch20 255 connection memory x x xx 6140 drw04 x channels xx streams x x 7 0,0 stream 2 stream 4 channel 20 channel 123 bpea = st4, ch20 bpsa = st2, ch12 3 255 x x x x x x x x x note: the group number is defined by the stream address in the bpsa. figure 1. group block programming
12 industrial temperature range idt72v73273 3.3v time slot interchange digital switch with rate matching 32,768 x 32,768 channels int st, ch for ( ch = startchannel; ch <= endchannel; ch++ ) { for ( st = startstream; st <= endstream; st++ ) { cmh [ st ][ ch ] = bpd; } } note: this code is for illustrations purposes only. the idt72v73273 is a hw instantiation of this kind of software. figure 2. "basic instantiation" /* groupnum is 0-7 */ /* groupdatarate = 2, 4, 8, 16. or 32 (2mb/s, 4mb/s, 8mb/s, 16mb/s, 32mb/s) */ functional blockprogram ( int groupnum; int groupdatarate ) { int st, ch; int maxstream = (( groupnum * 8 ) + 7 ) ; int maxchannel = ((( groupdatarate/2 ) * 32 ) - 1 ) ; /* startchannel <= endchannel */ if ( startchannel <= endchannel ){ for ( ch = startchannel; ch <= endchannel; ch++ ){ /* startstream <= endstream and startchannel <= endchannel */ if ( startstream <= endstream ){ for ( st = startstream; st <= endstream; st++ ){ cmh [ st ][ ch ] = bpd; } } /* startstream > endstream and startchannel <= endchannel */ else { for ( st = endstream; st <= maxstream; st++ ){ cmh [ st ] [ ch ] = bpd; } for ( st = ( groupnum*7 ) ; st <= startstream; st++ ){ cmh [ st ] [ ch ] = bpd; } } } } /* end > start channel */ else { /* the last part to be programmed */ for ( ch = endchannel; ch <= maxchannel; ch++ ){ /* startstream > endstream and startchannel > endchannel */ if ( startstream <= endstream ){ for ( st = startstream; st <= endstream; st++ ){ cmh [ st ] [ ch ] = bpd; } } /* startstream > endstream and startchannel > endchannel */ else { for ( st = endstream; st <= maxstream; st++ ){ chm [ st ] [ ch ] = bpd; } for (st = groupnum*7); st <= startstream; st++){ cmh [st] [ch] = bpd; } } ] /* the first part to be programmed */ for ( ch = 0; ch <= startchannel; ch++ ){ /* startstream > endstream and startchannel > endchannel */ if ( startstream <= endstream ){ for ( st = startstream; st <= endstream; st++ ){ cmh [ st ] [ ch ] = bpd; } } /* startstream > endstream and startchannel . endchannel */ else { for ( st = endstream; st <= maxstream; st++ ){ cmh [ st ] [ ch ] = bpd; } for ( st = ( groupnum*7 ) ; st <= startstream; st++ ){ cmh [ st ] [ ch ] = bpd; } } } } note: this code is for illustrations purposes only. the idt72v73273 is a hw instantiation of this software. figure 3. "real" instantiation of memory block programming
13 industrial temperature range idt72v73273 3.3v time slot interchange digital switch with rate matching 32,768 x 32,768 channels table 6 ? ber input selection register (bis) reset value: unknown (must be programmed) 1514131211109876543210 15 unused must be zero for normal operation 14-12 bg2-bg0 these bits refer to the input data group which receives the ber data. ((ber input group address bits) 11-9 bsa2-bsa0 these bits refer to the input data stream which receives the ber data. (ber input stream address bits) 8-0 bca8-bca0 these bits refer to the input channel which receives the ber data. (local ber input channel address bits) bit name description 0 bg2 bg1 bg0 bsa2 bsa1 bsa0 bca8 bca7 bca6 bca5 bca4 bca3 bca2 bca1 bca0 table 7 ? bit error rate register (berr) reset value: unknown (must be programmed) 1514131211109876543210 15-0 ber15-ber0 these bits refer to the local bit error counts. (local bit error rate count bits) bit name description ber15 ber14 ber13 ber12 ber11 ber10 ber9 ber8 ber7 ber6 ber5 ber4 ber3 ber2 ber1 ber0 bit err bit err bit err bit err bit err or ra or ra or ra or ra or ra te te te te te pseudo-random bit sequences (prbs) can be independently transmitted and received. by setting the connection memory high bits to the ber transmit mode, that particular channel will transmit a ber pattern of the form 2 15 -1. for the receiver only one channel can be specified and monitored at a given time. by setting the ber input selection (bis) to a given channel, every error in the ber sequence will be incremented by one. if the more than 2 16 -1 errors are encountered the berr register will automatically overflow and be reset to zero. it is important to note that no interrupt or warning will be issued in this case. it is recommended that this register be polled periodically and reset to prevent can overflow condition. to reset the pseudo-random bit sequence and the error count registers set the prst, cber, and sber of the control register to high. see the control register for details. following a write to the berr register a read of the berr will result in the present value of the berr data. likewise, when the clear bit rate bit (cber) in the control register is activated, this will clear the internal berr (iberr). as a general rule, a read of berr should be proceeded by a write to berr. again, it should be noted that the write to the berr register will actually initiate a transfer from the iberr to the berr while the microprocessor data is ignored. input frame offset selection input frame offset selection input frame offset selection input frame offset selection input frame offset selection input frame offset selection allows the channel alignment of individual input streams to be offset with respect to the output stream channel alignment. although all input data comes in at the same speed, delays can be caused by variable path serial backplanes and variable path lengths which may be implemented in large centralized and distributed switching systems. because data is often delayed, this feature is useful in compensating for the skew between input streams. each input stream can have its own delay offset value by programming the frame input offset registers (for, table 8). the maximum allowable skew is +7.5 clock periods forward with a resolution of ? clock period, see table 9. the output streams cannot be adjusted. note: before a read of the berr, a write to the berr is necessary. as a read only register the write will have no effect. see the bi t error rate section for mor details
14 industrial temperature range idt72v73273 3.3v time slot interchange digital switch with rate matching 32,768 x 32,768 channels table 8 ? frame input offset register (for) bits reset value: 0000 h . register 15 14 13 12 11 10 98765 43210 for0 register of32 of31 of30 dle3 of22 of21 of20 dle2 of12 of11 of10 dle1 of02 of01 of00 dle0 for1 register of72 of71 of70 dle7 of62 of61 of60 dle6 of52 of51 of50 dle5 of42 of41 of40 dle4 for2 register of112 of111 of110 dle11 of102 of101 of100 dle10 of92 of91 of90 dle9 of82 of81 of80 dle8 for3 register of152 of151 of150 dle15 of142 of141 of140 dle14 of132 of131 of130 dle13 of122 of121 of120 dle12 for4 register of192 of191 of190 dle19 of182 of181 of180 dle18 of172 of171 of170 dle17 od162 od161 of160 dle16 for5 register of232 of231 of230 dle23 of222 of221 of220 dle22 of212 of211 of210 dle21 of202 of201 of200 dle20 for6 register of272 of271 of270 dle27 of262 of261 of260 dle26 of252 of251 of250 dle25 of242 of241 of240 dle24 for7 register of312 of311 of310 dle31 of302 of301 of300 dle30 of292 of291 of290 dle29 of282 of281 of280 dle28 for8 register of352 of351 of350 dle35 of342 of341 of340 dle34 of332 of331 of330 dle33 of322 of321 of320 dle32 for9 register of392 of391 of390 dle39 of382 of381 of380 dle38 of372 of371 of370 dle37 of362 of361 of360 dle36 for10 register of432 of431 of430 dle43 of422 of421 of420 dle42 of412 of411 of410 dle41 of402 of401 of400 dle40 for11 register of472 of471 of470 dle47 of462 of461 of460 dle46 of452 of451 of450 dle45 of442 of441 of440 dle44 for12 register of512 of511 of510 dle51 of502 of501 of500 dle50 of492 of491 of490 dle49 of482 of481 of480 dle48 for13 register of552 of551 of550 dle55 of542 of541 of540 dle54 of532 of531 of530 dle53 of522 of521 of520 dle52 for14 register of592 of591 of590 dle59 of582 of581 of580 dle58 of572 of571 of570 dle57 of562 of561 of560 dle56 for15 register of632 of631 of630 dle63 of622 of621 of620 dle62 of612 of611 of610 dle61 of602 of601 of600 dle60 table 9 ? offset bits (ofn2, ofn1, ofn0, dlen) & frame delay bits (fd11, fd2-0) 32.768mb/s 16.384mb/s 8.192mb/s 4.096mb/s 2.048mb/s ofn2 ofn1 ofn0 dlen none none none none none 0 0 0 0 + 0.5 + 1.0 + 1.0 + 2.0 + 4.0 0 0 0 1 + 1.0 + 2.0 + 2.0 + 4.0 + 8.0 0 0 1 0 + 1.5 + 3.0 + 3.0 + 6.0 + 12.0 0 0 1 1 + 2.0 + 4.0 + 4.0 + 8.0 + 16.0 0 1 0 0 + 2.5 + 5.0 + 5.0 + 10.0 + 20.0 0 1 0 1 + 3.0 + 6.0 + 6.0 + 12.0 + 24.0 0 1 1 0 + 3.5 + 7.0 + 7.0 + 14.0 + 28.0 0 1 1 1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + 7.5 + 15.0 + 15.0 +30.0 + 60.0 1 1 1 1 i nput stream offset corresponding clock period shift based on 32.768mhz clock offset bits examples for input offset delay timing ofn2, ofn1, ofn0 these three bits define how long the serial interface receiver takes to recognize and store bit 0 from the rx i nput pin: i.e., to start a new frame. (offset bits 2, 1 & 0) the input frame offset can be selected to +7.5 clock periods from the point where the external frame puls e input signal is applied to the foi input of the device. dlen st-bus ? and dlen = 0, offset is on the clock boundary. (data latch edge) gci mode: dlen = 1, offset is a half cycle off of the clock boundary. name description
15 industrial temperature range idt72v73273 3.3v time slot interchange digital switch with rate matching 32,768 x 32,768 channels st-bus ? f32i rx stream @ 32mb/s bit 7 bit 7 c32i offset = 0, dle = 0 offset = 1, dle = 0 offset = 1, dle = 1 bit 6 bit 5 bit 5 rx stream @ 32mb/s offset = 0, dle = 0 bit 7 bit 6 rx stream @ 32mb/s bit 3 bit 3 bit 1 bit 4 rx stream @ 16mb/s bit 7 bit 5 rx stream @ 16mb/s rx stream @ 16mb/s rx stream @ 8mb/s rx stream @ 8mb/s rx stream @ 8mb/s rx stream @ 4mb/s rx stream @ 4mb/s rx stream @ 4mb/s bit 7 bit 7 bit 7 rx stream @ 2mb/s bit 7 bit 7 bit 7 bit 7 bit 1 bit 0 bit 4 bit 3 bit 2 bit 6 bit 5 bit 4 bit 3 bit 2 bit 6 bit 5 bit 4 bit 3 bit 6 bit 5 bit 6 bit 5 bit 6 bit 5 offset = 1, dle = 0 offset = 1, dle = 1 offset = 0, dle = 0 offset = 1, dle = 0 offset = 1, dle = 1 offset = 0, dle = 0 offset = 1, dle = 0 offset = 1, dle = 1 offset = 0, dle = 0 rx stream @ 2mb/s rx stream @ 2mb/s bit 7 bit 1 bit 1 bit 2 bit 4 bit 4 bit 4 bit 6 offset = 1, dle = 0 offset = 1, dle = 1 bit 5 bit 4 bit 2 bit 0 bit 6 bit 3 bit 2 bit 6 bit 4 bit 2 bit 1 bit 0 bit 1 bit 7 bit 0 bit 0 bit 0 bit 3 note: denotes sample point of rx data 16mhz clock 8mhz clock 4mhz clock bit 3 bit 5 bit 7 bit 6 bit 6 bit 6 bit 7 6140 drw05 figure 4. st-bus ? ? ? ? ? offset timing
16 industrial temperature range idt72v73273 3.3v time slot interchange digital switch with rate matching 32,768 x 32,768 channels gci bus f32i rx stream @ 32mb/s bit 7 bit 7 c32i offset = 0, dle = 0 offset = 1, dle = 0 offset = 1, dle = 1 bit 6 bit 6 bit 5 rx stream @ 32mb/s offset = 0, dle = 0 bit 7 bit 6 rx stream @ 32mb/s bit 5 bit 3 rx stream @ 16mb/s bit 7 bit 5 rx stream @ 16mb/s rx stream @ 16mb/s rx stream @ 8mb/s rx stream @ 8mb/s rx stream @ 8mb/s rx stream @ 4mb/s rx stream @ 4mb/s rx stream @ 4mb/s bit 7 bit 7 bit 7 rx stream @ 2mb/s bit 7 bit 7 bit 7 bit 7 bit 7 bit 2 bit 4 bit 3 bit 2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 6 bit 5 bit 4 bit 3 bit 6 bit 5 bit 6 bit 5 bit 6 bit 5 offset = 1, dle = 0 offset = 1, dle = 1 offset = 0, dle = 0 offset = 1, dle = 0 offset = 1, dle = 1 offset = 0, dle = 0 offset = 1, dle = 0 offset = 1, dle = 1 offset = 0, dle = 0 rx stream @ 2mb/s rx stream @ 2mb/s bit 1 bit 1 bit 2 bit 4 offset = 1, dle = 0 offset = 1, dle = 1 bit 4 bit 3 bit 0 bit 5 bit 4 bit 2 bit 1 bit 0 bit 6 bit 4 bit 3 bit 2 bit 1 bit 0 bit 4 bit 0 bit 1 bit 0 bit 1 bit 0 bit 3 bit 4 bit 6 bit 6 bit 7 16mhz clock 8mhz clock bit 6 bit 6 bit 7 4mhz clock denotes sample point of rx data 6140 drw06 figure 5. gci offset timing
17 industrial temperature range idt72v73273 3.3v time slot interchange digital switch with rate matching 32,768 x 32,768 channels set oe1 = 0 in tdrsr0 set oe1 = 1 in tdrsr0 f32i c32i tx0 tx8/oei0 o epol = 1 tx8/oei0 o epol = 0 6140 drw6 a ds bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 figure 6. the effect of enabling and disabling of the oe bit in tdrsr output enable indication the idt72v73273 has the capability to indicate the state of the outputs (active or three-state) by enabling the output enable indication in the drsr. in the output enable indication mode however, those output streams cannot be used to transmit cm or dm data only oe data. in the diagram below notice how the transmitting stream, tx0, is uneffected by the enabling and disabling of the oe stream (tx8). note: the tx0-7 pins are unaffected by the oe1 change.
18 industrial temperature range idt72v73273 3.3v time slot interchange digital switch with rate matching 32,768 x 32,768 channels figure 8. group oe operation bit 7 f32i c32i tx0 tx8-oei0 oepol =1 tx8-oei0 o epol = 0 123 4 5 678 6140 drw6 b bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 figure 7. group oe operation bit 7 f32i c32i tx0(-7) tx8-oei0 oepol =1 tx8-oei0 o epol = 0 6140 drw6 c bit 6 bit 5 bit 4 bit 4 bit 3 bit 2 bit 1 bit 0 ds set oe0 = 0 in tdrsr0 set oe0 = 1 in tdrsr0 note: group 0 is in 32mb/s and group 1 is in oei mode. note: the oei pins are unaffected by the oe0 change.
19 industrial temperature range idt72v73273 3.3v time slot interchange digital switch with rate matching 32,768 x 32,768 channels table 10 ? transmit data rate selection register (tdrsr) notes: 1. "x" corresponds to groups 0-7 (8 data streams per group). 2. if the gx2-0 are programmed to the reserved values the device will operate in the default 2.048mb/s mode. 3. only odd groups can be programmed for oei. the oei rate corresponds it's associated even group. reset value: 0000 h 1514131211109876543210 oe7 g72 g71 g70 oe6 g62 g61 g60 oe5 g52 g52 g51 oe4 g42 g41 g40 tx drsr 1 tx drsr 0 1514131211109 876543210 oe3 g32 g31 g30 oe2 g22 g21 g20 oe1 g12 g11 g10 oe0 g02 g01 g00 oex these bits can be used to high-z the entire associated group. if oex = 0 the group will be in high-z. if oex = 1, the grou p is in low-z (active state). gx2-gx0 these three group bits are used to select the transmit data rates for the eight groups of eight streams. see table 11 for data rates. gx2 (1) gx1 (1) gx0 (1) data rate 0 0 0 2.048mb/s 0 0 1 4.096mb/s 0 1 0 8.192mb/s 0 1 1 16.384mb/s 1 0 0 32.768mb/s 1 0 1 reserved (1) 1 1 0 reserved (1) 1 1 1 oei (1) group number streams speed with oei=1 g0 0-7 2.048mb/s-32.768mb/s 2.048mb/s-32.768mb/s g1 8-15 2.048mb/s-32.768mb/s oei<0-7> g2 16-23 2.048mb/s-32.768mb/s 2.048mb/s-32.768mb/s g3 24-31 2.048mb/s-32.768mb/s oei<16-23> g4 32-39 2.048mb/s-32.768mb/s 2.048mb/s-32.768mb/s g5 40-47 2.048mb/s-32.768mb/s oei<32-39> g6 48-55 2.048mb/s-32.768mb/s 2.048mb/s-32.768mb/s g7 56-63 2.048mb/s-32.768mb/s oei<48-55> table 11 ? tx grouping and data rates
20 industrial temperature range idt72v73273 3.3v time slot interchange digital switch with rate matching 32,768 x 32,768 channels reset value: 0000 h notes: 1. "x" corresponds to groups 0-7 (8 data streams per groupt). 2. if the gx2-0 are programmed to the reserved values the device will operated in the default 2.048b/s mode. 3. only odd groups can be programmed for oei. the oei rate corresponds to it's associated even group. table 12 ? receive data rate selection register(rdrsr) 1514131211109876543210 0 g72 g71 g70 0 g62 g61 g60 0 g52 g51 g50 0 g42 g41 g40 1514131211109876543210 0 g32 g31 g30 0 g22 g21 g20 0 g12 g11 g10 0 g02 g01 g00 rx drsr 1 rx drsr 0 gx0-gx2 these three group bits are used to select the receive data rates for the eight groups of eight streams. see table 13 for data rates. gx2 (1) gx1 (1) gx0 (1) data rate 0 0 0 2.048mb/s 0 0 1 4.096mb/s 0 1 0 8.192mb/s 0 1 1 16.384mb/s 1 0 0 32.768mb/s 1 0 1 reserved (1) 1 1 0 reserved (1) 1 1 1 reserved (1) table 13 ? rx grouping and data rates g0 0-7 2.048mb/s-32.768mb/s g1 8-15 2.048mb/s-32.768mb/s g2 16-23 2.048mb/s-32.768mb/s g3 24-31 2.048mb/s-32.768mb/s g4 32-39 2.048mb/s-32.768mb/s g5 40-47 2.048mb/s-32.768mb/s g6 48-55 2.048mb/s-32.768mb/s g7 56-63 2.048mb/s-32.768mb/s group number streams speed
21 industrial temperature range idt72v73273 3.3v time slot interchange digital switch with rate matching 32,768 x 32,768 channels table 14 ? connection memory high table 15 ? connection memory low notes: 1. when running the device at lower bit rates (i.e. 2, 4, 8, or 16mb/s), make sure the bits corresponding to the unused channels are set to 0. 2. all streams can run at 32.768mb/s simultaneously for the idt72v73273. 3. in processor mode, data in the lower byte (bits0-7) of the connection memory low will be outputted to the tx streams. the order in which the data are outputted will be starting from the lsb (bit 0) to the msb (bit 7) - the lower byte. the figure below illustrates the sequence: figure 9. processor mode bit sequencing reset value: unknown (must be programmed) 1514131211109876543210 reset value: unknown (must be programmed) 1514131211109876543210 15-3 unused must be zero for normal operation. 2-0 mod2-0 mod2 mod1 mod0 mode 0 0 0 variable delay mode 0 0 1 constant delay mode 0 1 0 reserved 0 1 1 reserved 1 0 0 processor mode 1 0 1 bit error rate test 1 1 0 reserved 1 1 1 high-impedance bit name description 15 unused must be zero for normal operation 14-9 sab5-0 the binary value is the number of the data stream for the source of the connection. (source stream address bits) 8-0 cab8-0 the binary value is the number of the channel for the source of the connection. (source channel address bits) bit name description 0 000000000000 mod2 mod1 mod0 0 sab5 sab4 sab3 sab2 sab1 sab0 cab8 cab7 cab6 cab5 cab4 cab3 cab2 cab1 cab0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 hg f e d c ba
22 industrial temperature range idt72v73273 3.3v time slot interchange digital switch with rate matching 32,768 x 32,768 channels ode 0 reset 1 c32i 2 f32i 3 s/ a 4 ds 5 cs 6 r/ w 7 a0 8 a1 9 a2 10 a3 11 a4 12 a5 13 a6 14 a7 15 a8 16 a9 17 a10 18 a11 19 a12 20 a13 21 a14 22 a15 23 bel 24 dta/beh 25 26 27 d15 28 29 30 d14 31 32 33 d13 34 35 36 d12 37 38 39 d11 40 41 42 d10 43 44 45 d9 46 47 48 d8 49 50 51 d7 52 53 54 d6 55 56 57 d5 58 59 60 d4 61 62 63 d3 64 65 66 d2 67 68 69 d1 70 71 72 d0 73 74 75 rx63 76 rx62 77 rx61 78 rx60 79 rx59 80 rx58 81 rx57 82 rx56 83 tx63/oei31 84 85 tx62/oei30 86 87 tx61/oei29 88 89 tx60/oei28 90 91 tx59/oei27 92 93 tx58/oei26 94 95 tx57/oei25 96 97 tx56/oei24 98 99 tx55/oei23 100 101 tx54/oei22 102 103 tx53/oei21 104 105 tx52/oei20 106 107 tx51/oei19 108 109 tx50/oei18 110 111 tx49/oe17 112 113 tx48/oei16 114 115 rx55 116 rx54 117 rx53 118 rx52 119 rx51 120 rx50 121 rx49 122 rx48 123 rx47 124 rx46 125 rx45 126 rx44 127 rx43 128 rx42 129 rx41 130 rx40 131 tx47/oei15 132 133 tx46/oei14 134 135 tx45/oei13 136 137 tx44/oei12 138 139 tx43/oei11 140 141 tx42/oei10 142 143 tx41/oei9 144 145 tx40/oei8 146 147 boundary scan bit 0 to 267 device pin input output three-state scan cell scan cell control table 16 ? boundary scan register bits boundary scan bit 0 to 267 device pin input output three-state scan cell scan cell control
23 industrial temperature range idt72v73273 3.3v time slot interchange digital switch with rate matching 32,768 x 32,768 channels tx39/oei7 148 149 tx38/oei6 150 151 tx37/oei5 152 153 tx36/oei4 154 155 tx35/oei3 156 157 tx34/oei2 158 159 tx33/oei1 160 161 tx32/oei0 162 163 rx39 164 rx38 165 rx37 166 rx36 167 rx35 168 rx34 169 rx33 170 rx32 171 rx31 172 rx30 173 rx29 174 rx28 175 rx27 176 rx26 177 rx25 178 rx24 179 tx31 180 181 tx30 182 183 tx29 184 185 tx28 186 187 tx27 188 189 tx26 190 191 tx25 192 193 tx24 194 195 tx23 196 197 tx22 198 199 tx21 200 201 tx20 202 203 tx19 204 205 tx18 206 207 tx17 208 209 tx16 210 211 rx23 212 rx22 213 rx21 214 rx20 215 rx19 216 rx18 217 rx17 218 rx16 219 rx15 220 rx14 221 rx13 222 rx12 223 rx11 224 rx10 225 rx9 226 rx8 227 tx15 228 229 tx14 230 231 tx13 232 233 tx12 234 235 tx11 236 237 tx10 238 239 tx9 240 241 tx8 242 243 tx7 244 245 tx6 246 247 tx5 248 249 tx4 250 251 tx3 252 253 tx2 254 255 tx1 256 257 tx0 258 259 rx7 260 rx6 261 rx5 262 rx4 263 rx3 264 rx2 265 rx1 266 rx0 267 table 16 ? boundary scan register bits (continued) boundary scan bit 0 to 267 device pin input output three-state scan cell scan cell control boundary scan bit 0 to 267 device pin input output three-state scan cell scan cell control
24 industrial temperature range idt72v73273 3.3v time slot interchange digital switch with rate matching 32,768 x 32,768 channels jtag support the idt72v73273 jtag interface conforms to the boundary-scan standard ieee-1149.1. this standard specifies a design-for-testability technique called boundary-scan test (bst). the operation of the boundary-scan circuitry is controlled by an external test access port (tap) controller. test access port (tap) the test access port (tap) provides access to the test functions of the idt72v73273. it consists of three input pins and one output pin. ?test clock input (tck) tck provides the clock for the test logic. the tck does not interfere with any on-chip clock and thus remains independent. the tck permits shifting of test data into or out of the boundary-scan register cells concurrently with the operation of the device and without interfering with the on-chip logic. ?test mode select input (tms) the logic signals received at the tms input are interpreted by the tap controller to control the test operations. the tms signals are sampled at the rising edge of the tck pulse. this pin is internally pulled to vcc when it is not driven from an external source. ?test data input (tdi) serial input data applied to this port is fed either into the instruction register or into a test data register, depending on the sequence previously applied to the tms input. both registers are described in a subsequent section. the received input data is sampled at the rising edge of tck pulses. this pin is internally pulled to vcc when it is not driven from an external source. ?test data output (tdo) depending on the sequence previously applied to the tms input, the contents of either the instruction register or data register are serially shifted out through the tdo pin on the falling edge of each tck pulse. when no data is shifted through the boundary scan cells, the tdo driver is set to a high-impedance state. table 17 ? identification register definitions instruction field value description revision number (31:28) 0x0 reserved for version number idt device id (27:12) 0x0430 defines idt part number idt jedec id (11:1) 0x33 allows unique identification of device vendor as idt id register indicator bit (bit 0) 1 indicates the presence of an id register register name bit size instruction (ir) 4 bypass (byr) 1 identification (idr) 32 boundary scan (bsr) note(1) table 18 ? scan register sizes notes: 1. the boundary scan descriptive language (bsdl) file for this device is available on the idt website (www.idt.com), or by contacting your local idt sales representative. ?test reset (trst) reset the jtag scan structure. this pin is internally pulled to vcc when it is not driven from an external source. instruction register in accordance with the ieee-1149.1 standard, the idt72v73273 uses public instructions. the idt72v73273 jtag interface contains a four-bit instruction register. instructions are serially loaded into the instruction register from the tdi when the tap controller is in its shift-ir state. subsequently, the instructions are decoded to achieve two basic functions: to select the test data register that may operate while the instruction is current, and to define the serial test data register path, which is used to shift data between tdi and tdo during data register scanning. see table 12 for instruction decoding. test data register as specified in ieee-1149.1, the idt72v73273 jtag interface contains two test data registers: ?the boundary-scan register the boundary-scan register consists of a series of boundary-scan cells arranged to form a scan path around the boundary of the idt72v73273 core logic. ?the bypass register the bypass register is a single stage shift register that provides a one-bit path from tdi to tdo. the idt72v73273 boundary scan register bits are shown in table 14. bit 0 is the first bit clocked out. all three-state enable bits are active high. id code register as specified in ieee-1149.1, this instruction loads the idr with the revision number, device id, jedec id, and id register indicator bit. see table 10.
25 industrial temperature range idt72v73273 3.3v time slot interchange digital switch with rate matching 32,768 x 32,768 channels tck tdi/tms (device inputs) (1) t jdc t js t jrsr t jf t jr x t jcl t jcyc t jch t jh t jcd t jrst tdo (device outputs) trst 6140 drw07 table 19 ? system interface parameters notes: 1. device outputs = all device outputs except tdo. 2. device inputs = all device inputs except tdi, tms and trst . instruction code description extest 0000 forces contents of the boundary scan cells onto the device outputs (1) . places the boundary scan register (bsr) between tdi and tdo. bypass 1111 places the bypass register (byr) between tdi and tdo. idcode 0010 lo ads the id register (idr) with the vendor id code and places the register between tdi and tdo. high-z 0011 places the bypass register (byr) between tdi and tdo. forces all device output drivers to a high-z state. sample/preload 0001 places the boundary scan register (bsr) between tdi and tdo. sample allows data from device inputs (2) and outputs (1) to be captured in the boundary scan cells and shifted serially through tdo. preload allows data to be input serially into the boundar y scan cells via the tdi. reserved all other codes several combinations are reserved. do not use other codes than those identified above. symbol parameter min. max. units t jcyc jtag clock input period 100 ? ns t jch jtag clock high 40 ? ns t jcl jtag clock low 40 ? ns t jr jtag clock rise time ? 3 (1) ns t jf jtag clock fall time ? 3 (1) ns t jrst jtag reset 50 ? ns t jrsr jtag reset recovery 50 ? ns t jcd jtag data output ? 25 ns t jdc jtag data output hold 0 ? ns t js jtag setup 15 ? ns t jh jtag hold 15 ? ns table 20 ? jtag ac electrical characteristics (1,2,3,4) notes: 1. guaranteed by design. 2. 30pf loading on external output signals. 3. refer to ac electrical test conditions stated earlier in this document. 4. jtag operations occur at one speed (10mhz). the base device may run at any speed specified in this datasheet. figure 10. jtag timing specifications note: 1. device inputs = all device inputs except tdi, tms and trst .
26 industrial temperature range idt72v73273 3.3v time slot interchange digital switch with rate matching 32,768 x 32,768 channels symbol parameter min. typ. max. units i cc (2) supply current ?? 380 ma i il (3,4) input leakage (input pins) ? ? 60 a i bl (3,4) input leakage (i/o pins) ? 60 a i oz (3,4) high-impedance leakage ?? 60 a v oh (5) output high voltage 2.4 ?? v v ol (6) output low voltage ?? 0.4 v dc electrical characteristics notes: 1. voltages are with respect to ground (gnd) unless otherwise stated. 2. outputs unloaded. 3. 0 v v cc . 4. maximum leakage on pins (output or i/o pins in high-impedance state) is over an applied voltage (v). 5. ioh = 10 ma. 6. iol = 10 ma. symbol parameter min. max. unit v cc supply voltage -0.5 +4.0 v vi voltage on digital inputs gnd -0.3 v cc +0.3 v i o current at digital outputs -50 50 ma t s storage temperature -55 +125 c p d package power dissapation ? 2w note: 1. exceeding these values may cause permanent damage. functional operation under these conditions is not implied. absolute maximum ratings (1) recommended operating conditions (1) symbol parameter min. typ. max. unit v cc positive supply 3.0 3.3 3.6 v v ih (1) input high voltage 2.0 ? v cc v v il input low voltage -0.3 ? 0.8 v t op operating temperature -40 25 +85 c industrial ac electrical characteristics - timing parameter measurement voltage levels symbol rating level unit v tt ttl threshold 1.5 v v hm ttl rise/fall threshold voltage high 2.0 v v lm ttl rise/fall threshold voltage low 0.8 v input pulse levels v tr,tf input rise/fall times 1 ns input timing reference levels v output reference levels v c l (1) output load 50 pf note: 1. jtag c l is 30pf 6140 drw0 8 50 ? v dd i/o z0 = 50 ? 6140 drw09 330 ? 30pf* 510 ? 3.3v d .u.t. figure 11. ac termination figure 12. ac test load not yet characterized not yet characterized notes: 1. input/outputs are not 5v tolerant. 2. voltages are with respect to ground (gnd) unless otherwise stated.
27 industrial temperature range idt72v73273 3.3v time slot interchange digital switch with rate matching 32,768 x 32,768 channels ac electrical characteristics - reset and ode timing symbol parameter min. typ. max. units t odlez output driver enable (ode) to low-z 6 ? ? ns t rs reset pulse width 20 ? ? ns t rz active to high-z on master reset ? ? 12 ns reset tx ode t rs t zr t rz t rz t odelz 6140 drw10 t ode (1) figure 13. reset and ode timing figure 15. output driver enable (ode) o de tx valid data 6140 drw12 t odelz t odehz t odea c 32i (st-bus ? mode) tx tx valid data valid data c32i (gci mode) 6140 drw1 1 t chz t clz t sod t sih figure 14. serial output and external control ac electrical characteristics - c32i and ode to high-z timing and c32i and ode to low-z timing symbol parameter min. typ. max. units t clz (1) clock to low-z 3 ? ? ns t chz (1) clock to high-z ? ? 9 ns t odea ode to valid data 6 ? ? ns t odehz output driver enable (ode) to high-z 3 ? 9 ns t odelz output driver enable (ode) to low-z 4 ? ? ns t sih (1) rx hold time 4 ? ? ns t sod clock to valid data 3 7 9 ns note: 1. c l = 30pf
28 industrial temperature range idt72v73273 3.3v time slot interchange digital switch with rate matching 32,768 x 32,768 channels ac electrical characteristics - st-bus ? timing symbol parameter min. typ. max. u nits t ch c32i pulse width high clock rate = 32.768mb/s 13 15.25 17 ns t cl c32i pulse width low clock rate = 3.2768mb/s 13 15.25 17 ns t cp c32i period clock rate = 32.768mb/s 29 30.5 35 ns t fph frame pulse hold time from c32i falling (st-bus ? or gci) 5 ? ? ns t fps frame pulse setup time before c32i falling (st-bus ? or gci) 5 ? ? ns t fpw frame pulse width (st-bus ? , gci) clock rate = 32.768mb/s 13 ? 31 ns tr,tf (1) clock rise/fall time ? 1 ? ns t sih rx hold time 4 ? ? ns t sis rx setup time 2 ? ? ns t sod clock to valid data 3 7 9 ns note: 1. parameters verified under test conditions. t cp t ch t cl t sis t sih rx 8.192 mb/s t sis t sih bit 7 bit 6 bit 5 bit 4 bit 0 tx 8.192 mb/s t sod t cl t cp bit 7 bit 0 bit 6 bit 5 bit 4 bit 3 c lk-16.384 mhz (1) t ch tx 4.096 mb/s rx 4.096 mb/s bit 7 bit 0 bit 6 bit 5 t sis t sih bit 7 bit 6 bit 0 t sod clk- 8.192 mhz (1) t cp t cl tx 16.384 mb/s rx 16.384 mb/s bit 7 t sod bit 0 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 0 bit 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 1 bit 0 t fpw t fph t fps f32i c32i tx 32.768 mb/s rx 32.768 mb/s bit 7 bit 0 t sis t sih bit 7 t sod bit 1 bit 2 bit 5 bit 6 bit 3 bit 4 bit 1 bit 2 bit 7 bit 0 bit 5 bit 6 bit 3 bit 4 bit 1 bit 2 bit 7 bit 0 bit 0 bit 1 bit 2 bit 5 bit 6 bit 3 bit 4 bit 1 bit 2 bit 7 bit 0 bit 5 bit 6 bit 3 bit 4 bit 1 bit 2 bit 7 bit 0 t r t f t sod clk- 4.096 mhz (1) tx 2.048 mb/s bit 0 rx 2.048 mb/s bit 7 bit 6 t sis t sih bit 7 bit 7 t ch 6140 drw13 figure 16 st-bus ? ? ? ? ? timing note: 1. these clocks are for reference purposes only. the tsi only accepts a 32.768mhz clock.
29 industrial temperature range idt72v73273 3.3v time slot interchange digital switch with rate matching 32,768 x 32,768 channels t sis t sih bit 7 bit 6 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 t sis t sih bit 0 bit 1 bit 2 bit 3 bit 7 tx 8.192 mb/s rx 8.192 mb/s bit 0 bit 7 bit 1 bit 2 bit 3 t sod c lk- 16.384 mhz (1) t ch t cl t cp 6140 drw1 4 bit 0 bit 1 bit 7 t sis t sih bit 0 bit 7 bit 1 t sod tx 4.096 mb/s rx 4.096 mb/s clk- 8.192 mhz (1) t cp t ch t cl tx 16.384 mb/s rx 16.384 mb/s bit 0 bit 7 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 6 t sod tx 32.768 mb/s rx 32.768 mb/s t fpw t fph t r t f t fps f32i clk- 32.768 mhz t sis t sih bit 0 bit 0 t sod bit 7 bit 6 bit 5 bit 3 bit 2 bit 1 bit 6 bit 5 bit 4 bit 1 bit 0 bit 7 bit 4 bit 3 bit 2 bit 7 bit 6 bit 5 bit 7 bit 6 bit 3 bit 2 bit 1 bit 6 bit 5 bit 4 bit 1 bit 0 bit 7 bit 4 bit 3 bit 2 bit 7 bit 6 bit 5 t cp t ch t cl tx 2.048 mb/s rx 2.048 mb/s clk- 4.096 mhz (1) bit 0 bit 7 t sod bit 0 t sis t sih figure 17. gci bus timing note: 1. these clocks are for reference purposes only. the tsi only accepts a 32.768mhz clock. ac electrical characteristics - gci bus timing symbol parameter min. typ. max. units t ch c32i pulse width high clock rate = 32.768mb/s 13 15.25 17 ns t cl c32i pulse width low clock rate = 32.768mb/s 13 15.25 17 ns t cp c32i period clock rate = 32.768mb/s 29 30.5 35 ns t fph frame pulse hold time from c32i falling (st-bus ? or gci) 5 ? ? ns t fps frame pulse setup time before c32i falling (st-bus ? or gci) 5 ? ? ns t fpw frame pulse width (st-bus ? , gci) clock rate = 32.768mb/s 13 ? 31 ns tr,tf clock rise/fall time ? 1 ? ns t sih rx hold time 4 ? ? ns t sis rx setup time 2 ? ? ns t sod clock to valid data 3 7 9 ns
30 industrial temperature range idt72v73273 3.3v time slot interchange digital switch with rate matching 32,768 x 32,768 channels t cp t ch t cl t r t f t fpw t fph t fps f32i c32i 6140 drw1 5 bit 5 bit 6 bit 7 bit 4 t sod bit 1 bit 2 bit 3 bit 0 t clz t x16.384 mb/s t oeie t oeie oei (1) t oeid t oeid t chz oei (2) figure 18. oei bus timing in st-bus ? ? ? ? ? mode notes: 1. oepol = 1 2. oepol = 0 ac electrical characteristics - oei bus timing in st-bus ? mode symbol parameter min. typ. max. units t ch c32i pulse width high clock rate = 32.768mb/s 13 15.25 17 ns t chz (2) clock to high-z ? ? 9 ns t cl c32i pulse width low clock rate = 32.768mb/s 13 15.25 17 ns t clz (2) clock to low-z 3 ? ? ns t cp c32i period clock rate = 32.768mb/s 29 30.5 35 ns t fph frame pulse hold time from c32i falling (st-bus ? or gci) 5 ? ? ns t fps frame pulse setup time before c32i falling (st-bus ? or gci) 5 ? ? ns t fpw frame pulse width (st-bus ? , gci) clock rate = 32.768mb/s 13 ? 31 ns t oeie clock to oei enable 3 ? 9 ns t oeid clock to oei disable 3 ? 9 ns t r, t f (1) clock rise/fall time ? 1 ? ns t sod clock to valid data 3 7 9 ns notes: 1. parameters verified under test conditions. 2. c l = 300pf
31 industrial temperature range idt72v73273 3.3v time slot interchange digital switch with rate matching 32,768 x 32,768 channels figure 19 . rx to tx internal bypass bit ac electrical characteristics - rx to tx internal bypass bit symbol parameter min. typ. max. u nits t bc 2812ns r x t x t bc 6140 drw16 t bc = end to end chip delay t bc t bc
32 industrial temperature range idt72v73273 3.3v time slot interchange digital switch with rate matching 32,768 x 32,768 channels symbol parameter min. typ. max. units t adh address hold after ds rising 2 ? ? ns t ads address setup from ds falling 2 ? ? ns t akd (1) acknowledgement delay: reading/writing memory ? ? 30 ns t akh (1,2,3) acknowledgement hold time ? ? 10 ns t csh cs hold after ds rising 0 ? ? ns t css cs setup from ds falling 0 ? ? ns t ddr (1) data setup from dta low on read 2 ? ? ns t dhr (1,2,3) data hold on read 10 15 25 ns t dhw data hold on write 5 ? ? ns t dss data strobe setup time 2 ? ? ns t dspw data strobe pulse width 6 ? ? ns t rwh r/ w hold after ds rising 3 ? ? ns t rws r/ w setup from ds falling 3 ? ? ns t swd valid data delay on write 2 ? ? ns notes: 1. c l = 30pf 2. r l = 1k 3. high-impedance is measured by pulling to the appropriate rail with r l , with timing corrected to cancel time taken to discharge c l . 4. to achieve on clock cycle fast memory access, this setup time, t dss should be met. otherwise, worst-case memory access operation is determined by t akd . ac electrical characteristics - motorola non-multiplexed bus asychronous timing memory access ds cs valid write address a0-a15 t css t csh r/ w t rws t rwh t ads t adh valid write data d0-d15 t dhw dta t akd t akh t css t csh t rws t rwh valid read address t ads t adh valid read data t ddr t dhr t akd t akh 6140 drw17 c lk st-bus ? t dss clk gci t dss t dspw t swd figure 20. motorola non-multiplexed bus asychronous timing memory access
33 industrial temperature range idt72v73273 3.3v time slot interchange digital switch with rate matching 32,768 x 32,768 channels ds cs valid write address a 0-a15 t css t csh r/ w t rws t rwh t ads t adh valid write data d 0-d15 t dsw t dhw dta t akd t akh t css t csh t rws t rwh valid read address t ads t adh valid read data t ddr t dhr t akd t akh 6140 drw17 a t dspw figure 21. motorola non-multiplexed bus asychronous timing register access symbol parameter min. typ. max. units t adh address hold after ds rising 2 ? ? ns t ads address setup from ds falling 2 ? ? ns t akd (1) acknowledgement delay: reading/writing registers ? ? 40 ns t akh (1,2,3) acknowledgement hold time ? ? 20 ns t csh cs hold after ds rising 0 ? ? ns t css cs setup from ds falling 0 ? ? ns t ddr (1) data setup from dta low on read 2 ? ? ns t dhr (1,2,3) data hold on read 10 15 25 ns t dhw data hold on write 5 ? ? ns t dspw data strobe pulse width 6 ? ? ns t dsw data setup on write 10 ? ? ns t rwh r/ w hold after ds rising 3 ? ? ns t rws r/ w setup from ds falling 3 ? ? ns notes: 1. c l = 30pf 2. r l = 1k 3. high-impedance is measured by pulling to the appropriate rail with r l , with timing corrected to cancel time taken to discharge c l . 4. to achieve on clock cycle fast memory access, this setup time, t dss should be met. otherwise, worst-case memory access operation is determined by t akd . ac electrical characteristics - motorola non-multiplexed bus asychronous timing register access
34 industrial temperature range idt72v73273 3.3v time slot interchange digital switch with rate matching 32,768 x 32,768 channels clk gci cs ben r/w a0-15 data-in data-out t scss t scsh t bes t beh t rws t rwh read t cd t dhr qn dn t rws t dhw t rwh write 6140 drw1 8 t scss t scsh t bes t beh t dsw c lk st-bus ? t ads t adh t ads t adh figure 22. synchronous bus timing symbol parameter min. typ. max. units t adh address hold 3? ? ns t ads address setup 3? ? ns t beh byte enable hold 3 ? ? ns t bes byte enable setup 3 ? ? ns t cd clock to data ?? 20 ns t dhr (1,2,3) data hold on read 10 15 25 ns t dhw data hold on write 3 ? ? ns t dsw data setup on write 3 ? ? ns t rwh r/ w hold 3? ? ns t rws r/ w setup 3? ? ns ts csh cs hold 3? ? ns ts css cs setup 3? ? ns ac electrical characteristics - synchronous bus timing notes: 1. c l = 30pf 2. r l = 1k 3. high-impedance is measured by pulling to the appropriate rail with r l , with timing corrected to cancel time taken to discharge c l .
35 industrial temperature range idt72v73273 3.3v time slot interchange digital switch with rate matching 32,768 x 32,768 channels d8-15 d8-15 t cd 6140 drw19 a0-15 (3) read read clk gci cs bel beh t scss t scsh t bes t beh t scss t beh r/w t rws t rwh t rws t rwh t ads t adh d0-7 t dhr d0-7 t cd t dhr clk st-bus ? t ads t adh t bes t scsh figure 23. byte enable symbol parameter min. typ. max. units t adh address hold 3? ? ns t ads address setup 3? ? ns t beh byte enable hold 3 ? ? ns t bes byte enable setup 3 ? ? ns t cd clock to data ?? 20 ns t dhr (1,2,3) data hold on read 10 15 25 ns t rwh r/ w hold 3? ? ns t rws r/ w setup 3? ? ns ts csh cs hold 3? ? ns ts css cs setup 3? ? ns ac electrical characteristics - byte enable notes: 1. c l = 30pf 2. r l = 1k 3. high-impedance is measured by pulling to the appropriate rail with r l , with timing corrected to cancel time taken to discharge c l .
36 corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 408-330-1753 santa clara, ca 95054 fax: 408-492-8674 email: telecomhelp@idt.com www.idt.com ordering information 6140 drw22 xxxxxx device type x package process/ temperature range xx blank commercial (-40 c to +85 c) 72v73273 32,768 x 32,768 ? 3.3v time slot interchange digital switch with rate matching bb dr plastic ball grid array (pbga, bb208-1) plastic quad flatpack (pqfp, dr208-1) datasheet document history 06/30/2003 pgs. 9,14, 33 and 34. 09/08/2003 pgs. 1, 4, 20, 28, 33 and 34. 10/28/2003 pg. 1. 02/09/2009 pg. 36 removed idt from orderable part number

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